Functional Verification of Power Gated Designs by Compositional Reasoning 1st edtion by Cindy Eisner, Amir Nahir, Karen Yorav ISBN 3540705437 9783540705437

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Product details:

ISBN 10:       3540705437
ISBN 13: 978-3540705437
Author:       Cindy Eisner, Amir Nahir, Karen Yorav  

Power gating is a technique for low power design in which whole sections of the chip are powered off when they are not needed, and powered back on when they are. Functional correctness of power gating is usually checked as part of system-level verification, where the most widely used technique is simulation using pseudo-random stimuli. We propose instead to perform a sequential equivalence check between the power gated design and a version of itself in which power gating is disabled. We take a compositional approach that looks for partial equivalence of each unit under a suitable set of assumptions, guaranteed by the neighboring units. We make use of so-called circular reasoning rules to compose the partial equivalences proved on the individual units back into total equivalence on the whole chip.

Functional Verification of Power Gated Designs by Compositional Reasoning 1st  Table of contents:

Chapter 1: Introduction
1.1 Overview of Power Gated Designs
1.2 Challenges in Functional Verification of Power Gated Systems
1.3 Introduction to Compositional Reasoning
1.4 Motivation for Functional Verification in Power Gated Designs
1.5 Objectives and Scope of the Paper
1.6 Structure of the Paper

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Chapter 2: Background and Related Work
2.1 Power Gating: Principles and Techniques
2.2 Functional Verification: Definitions and Approaches
2.3 Verification Challenges in Low-Power Design
2.4 Compositional Reasoning in System Verification
2.5 Previous Work on Power Gated Design Verification

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Chapter 3: Power Gated Designs
3.1 Definition and Benefits of Power Gating
3.2 Types of Power Gating Techniques
3.3 Key Challenges in Power Gated Systems
3.4 Impact of Power Gating on Design Complexity
3.5 Power Gating and Low-Power Design Strategies

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Chapter 4: Compositional Reasoning in Verification
4.1 Overview of Compositional Reasoning
4.2 Compositional Reasoning in System Design and Verification
4.3 Decomposition Techniques for Complex Systems
4.4 Modular Verification Approaches
4.5 Advantages and Challenges of Compositional Reasoning

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Chapter 5: Functional Verification Methodology for Power Gated Designs
5.1 Functional Verification Requirements for Power Gated Designs
5.2 Integrating Compositional Reasoning with Power Gated Design Verification
5.3 Step-by-Step Methodology for Verification
5.4 Decomposing Power Gated Systems for Modular Verification
5.5 Handling Power Domains in Verification

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Chapter 6: Algorithmic Approaches to Compositional Verification
6.1 Compositional Verification Algorithms
6.2 Automated Verification of Power Gated Designs
6.3 Combining State-Space Decomposition with Compositional Reasoning
6.4 Efficient Algorithms for Verifying Power Gated Systems
6.5 Complexity Analysis of Verification Algorithms

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Chapter 7: Case Studies and Applications
7.1 Case Study: Functional Verification in Power Gated Processors
7.2 Verification of Power Gated Memory Systems
7.3 Application of Compositional Reasoning in SOC Designs
7.4 Results of Power Gating Functional Verification in Real-World Systems
7.5 Lessons Learned from Industry Implementations

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Chapter 8: Verification Tool Support
8.1 Overview of Verification Tools for Power Gated Designs
8.2 Tool Integration for Compositional Reasoning
8.3 Automating Functional Verification with Tools
8.4 Tool-Based Case Studies in Power Gating
8.5 Challenges in Tool Support for Power Gated Designs

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Chapter 9: Open Problems and Future Directions
9.1 Unsolved Problems in Functional Verification of Power Gated Designs
9.2 Scalability Issues with Compositional Verification
9.3 Future Directions in Power Gating and Verification Techniques
9.4 The Role of Machine Learning and AI in Verification
9.5 Towards Fully Automated Power Gated Design Verification

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Chapter 10: Conclusion
10.1 Summary of Key Contributions
10.2 Impact of Compositional Reasoning on Power Gated Design Verification
10.3 Final Thoughts on Power Gating and Functional Verification
10.4 Concluding Remarks on Future Research in Design Verification

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