Designing Digital Computer Systems with Verilog 1st Edition by David Lilja, Sachin Sapatnekar ISBN 0511261667 9780511261664

Designing Digital Computer Systems with Verilog 1st Edition by David J. Lilja, Sachin S. Sapatnekar – Ebook PDF Instant Download/Delivery. 0511261667, 9780511261664

Full download Designing Digital Computer Systems with Verilog 1st Edition after payment

 

 

Product details:

ISBN 10: 0511261667

ISBN 13: 9780511261664

Author:  David J. Lilja, Sachin S. Sapatnekar 

Designing Digital Computer Systems with Verilog 1st Edition: Using Verilog, a leading commercial hardware description language, this text describes how to specify, design, and test a complete digital system. After a brief introduction to the Verilog language, the instruction set architecture (ISA) for the simple VeSPA (Very Small Processor Architecture) processor is defined. The remainder of the book demonstrates how both behavioral and structural models can be developed and intermingled in Verilog.

 

Designing Digital Computer Systems with Verilog 1st Edition Table of contents:

1 Controlling Complexity

• Hierarchical design flow
• Designing hardware with software
• Summary

2 A Verilogical Place to Start

• My Veri first description
• A more formal introduction to the basics
  • Modules and ports
  • Nets and registers
  • Vectors and arrays
  • Constants
  • Number representation
  • Operators
• Behavioral and structural models
  • An example of a finite state machine
  • Behavioral modeling
  • Other constructs for behavioral modeling
    • Timing controls
    • Blocking and nonblocking assignments
    • Loops
  • Structural description
• Functions and tasks
• Summary
• Further reading

3 Defining the Instruction Set Architecture

• Instruction set design
• Defining the VeSPA instruction set
  • Arithmetic instructions
    • Specifying operands
    • Choosing specific instructions
    • Arithmetic overflow
    • Arithmetic carry out
  • Logical operation instructions
  • Control instructions
    • Condition codes
    • Setting the condition codes
    • Conditional branching
  • Data transfer instructions
    • Load-store and memory-to-memory architectures
    • The VeSPA load-store instructions
  • Miscellaneous instructions
• Specifying the VeSPA ISA
  • The instruction format
  • Instruction specifications
    • Arithmetic and logical instructions
    • Control instructions
    • Data transfer instructions
    • Miscellaneous instructions
• Summary
• Further reading

4 Algorithmic Behavioral Modeling

• Module definition
• Instruction and storage element definitions
  • Parameters
  • Register declarations
  • Instruction field and opcode definitions
• Fetch-execute loop
• Fetch task
  • Memory interface
• Execute task
• Condition code tasks
• Tracing instruction execution
• Summary

5 Building an Assembler for VeSPA

• Why assembly language?
• The assembly process
  • Assembly language format
  • Two-pass assembler
• VASM – the VeSPA assembler
  • VASM syntax and assembler commands
  • Pass 1 – lexical analysis and parsing
  • Pass 2 – machine code generation
• Linking and loading
• Summary

6 Pipelining

• Instruction partitioning for pipelining
• Pipeline performance
• Dependences and hazards
  • Program dependences
    • Control dependences
    • Data dependences
  • Pipeline hazards
    • Branch hazards
    • Data hazards
    • Structural hazards
• Dealing with pipeline hazards
• Summary
• Further reading

7 Implementation of the Pipelined Processor

• Pipelining VeSPA
• The hazard detection unit
• Overview of the pipeline structure
• A detailed description of the pipeline stages
  • The instruction fetch (IF) stage
  • The instruction decode (ID) stage
  • The execute (EX) stage
  • The memory access (MEM) and write back (WB) stages
• Timing considerations
• Summary
• Further reading

8 Verification

• Component-level test benches
  • Using manually generated test vectors
  • Using automatically generated test vectors
  • Constrained pseudorandom test vectors
  • Initialization
• System-level self-testing
  • Initial steps
  • Program structure
• Formal verification
• Summary

 

People also search for Designing Digital Computer Systems with Verilog 1st Edition:

digital systems design using verilog solution manual pdf
    
digital system design verilog
    
digital design with system verilog
    
digital integrated circuit design using verilog and systemverilog
    
digital design with verilog