Design Methodology for RF CMOS Phase Locked Loops 1st Edition by Carlos Quemada, Guillermo Bistuae, Ianigo Adin ISBN 1596933844 9781596933842

Design Methodology for RF CMOS Phase Locked Loops 1st Edition by Carlos Quemada, Guillermo Bistuae, Ianigo Adin – Ebook PDF Instant Download/Delivery. 1596933844, 9781596933842

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Product details:

ISBN 10: 1596933844

ISBN 13: 9781596933842

Author:  Carlos Quemada, Guillermo Bistuae, Ianigo Adin 

Design Methodology for RF CMOS Phase Locked Loops 1st Edition: Blast through phase-locked loop challenges fast with this practical book guiding you every step of the way from specs definition to layout generation. You get a proven PLL design and optimization methodology that lets you systematically assess design alternatives, predict PLL behavior, and develop complete PLLs for CMOS applications that meet performance requirements no matter what IC challenges you come up against. After a review of PLL essentials, this uniquely comprehensive workbench guide takes you step-by-step through operation principles, design procedures, phase noise analysis, layout considerations, and CMOS realizations for each PLL building block. You get full details on LC tank oscillators including modeling and optimization techniques, followed by design options for CMOS frequency dividers covering flip-flop implementation, the divider by 2 component, and other key factors. The book includes design alternatives for phase detectors that feature methods to minimize jitter caused by the dead zone effect. You also find a sample design of a fully integrated PLL for WLAN applications that demonstrates every step and detail right down to the circuit schematics and layout diagrams. Supported by over 150 diagrams and photos, this one-stop toolkit helps you produce superior PLL designs faster, and deliver more effective solutions for low-cost integrated circuits in all RF applications.

 

Design Methodology for RF CMOS Phase Locked Loops 1st Edition Table of contents:

Approach to CMOS PLL Design

• MOS Transistor Basics Review
• Non-ideal and Second Order Effects in Sub-micron Technologies
• Impact on PLL Performance
• State-of-the-art and Challenges in CMOS PLL Design
• PLL Design Flow

PLL Fundamentals

• Basic Architectures
• Figures of Merit

LC Tank Voltage Controlled Oscillator

• VCO Basics
• CMOS LC Tank Oscillators
• Passive Components Modeling and Characterization
• VCO Phase Noise
• Layout Considerations

Frequency Divider

• Design Alternatives
• Divider by 2
• Dual-Modulus Prescaler
• Low Frequency Dividers
• Phase Noise
• Layout Considerations

Phase Detector

• Multipliers
• Exclusive-Or Gate
• Flip-Flops
• Phase-Frequency Detector and Charge Pump
• Phase Noise
• Layout Considerations

Design of a Fully Integrated PLL for WLAN Applications

• System Analysis
• Building Block Specifications
• Schematic Circuit Design
• PLL Layout Considerations

Characterization

• Experimental Setup
• Results

 

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