Computer Organization and Design The Hardware Software Interface 5th Edition by David A Patterson, John L Hennessy ISBN 0124077269 9780124077263

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ISBN 10: 0124077269 
ISBN 13: 9780124077263
Author: David A Patterson, John L Hennessy

The 5th edition of Computer Organization and Design moves forward into the post-PC era with new examples, exercises, and material highlighting the emergence of mobile computing and the cloud. This generational change is emphasized and explored with updated content featuring tablet computers, cloud infrastructure, and the ARM (mobile computing devices) and x86 (cloud computing) architectures.

Because an understanding of modern hardware is essential to achieving good performance and energy efficiency, this edition adds a new concrete example, “Going Faster,” used throughout the text to demonstrate extremely effective optimization techniques. Also new to this edition is discussion of the “Eight Great Ideas” of computer architecture.

As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, computer arithmetic, pipelining, memory hierarchies and I/O.

Instructors looking for 4th Edition teaching materials should e-mail [email protected]

• Includes new examples, exercises, and material highlighting the emergence of mobile computing and the Cloud.
• Covers parallelism in depth with examples and content highlighting parallel hardware and software topics
• Features the Intel Core i7, ARM Cortex-A8 and NVIDIA Fermi GPU as real-world examples throughout the book
• Adds a new concrete example, “Going Faster,” to demonstrate how understanding hardware can inspire software optimizations that improve performance by 200 times.
• Discusses and highlights the “Eight Great Ideas” of computer architecture:  Performance via Parallelism; Performance via Pipelining; Performance via Prediction; Design for Moore’s Law; Hierarchy of Memories; Abstraction to Simplify Design; Make the Common Case Fast;  and Dependability via Redundancy.
• Includes a full set of updated and improved exercises.

 Computer Organization and Design The Hardware Software Interface 5th Table of contents:

1. Computer Abstractions and Technology
1.1 Introduction
1.2 Eight Great Ideas in Computer Architecture
1.3 Below Your Program
1.4 Under the Covers
1.5 Technologies for Building Processors and Memory
1.6 Performance
1.7 The Power Wall
1.8 The Sea Change: The Switch from Uniprocessors to Multiprocessors
1.9 Real Stuff: Benchmarking the Intel Core i7
1.10 Fallacies and Pitfalls
1.11 Concluding Remarks
Historical Perspective and Further Reading
1.13 Exercises
1. Solutions
Historical Perspective and Further Reading
The First Electronic Computers
Commercial Developments
Measuring Performance
The Quest for an Average Program
SPECulating about Performance
The Growth of Embedded Computing
A Half-Century of Progress
Further Reading
2. Instructions: Language of the Computer
2.1 Introduction
2.2 Operations of the Computer Hardware
2.3 Operands of the Computer Hardware
2.4 Signed and Unsigned Numbers
2.5 Representing Instructions in the Computer
2.6 Logical Operations
2.7 Instructions for Making Decisions
2.8 Supporting Procedures in Computer Hardware
2.9 Communicating with People
2.10 MIPS Addressing for 32-bit Immediates and Addresses
2.11 Parallelism and Instructions: Synchronization
2.12 Translating and Starting a Program
2.13 A C Sort Example to Put It All Together
2.14 Arrays versus Pointers
Advanced Material: Compiling C and Interpreting Java
2.16 Real Stuff: ARMv7 (32-bit) Instructions
2.17 Real Stuff: x86 Instructions
2.18 Real Stuff: ARMv8 (64-bit) Instructions
2.19 Fallacies and Pitfalls
2.20 Concluding Remarks
Historical Perspective and Further Reading
2.22 Exercises
2. Solutions
Advanced Material: Compiling C and Interpreting Java
Compiling C
The Front End
High-Level Optimizations
Local and Global Optimizations
Global Code Optimizations
Implementing Local Optimizations
Implementing Global Optimizations
Register Allocation
Code Generation
Optimization Summary
Interpreting Java
Interpretation
Compiling for Java
Invoking Methods in Java
A Sort Example in Java
Historical Perspective and Further Reading
Accumulator Architectures
General-Purpose Register Architectures
Compact Code and Stack Architectures
High-Level-Language Computer Architectures
Reduced Instruction Set Computer Architectures
A Brief History of the ARM
A Brief History of the x86
A Brief History of Programming Languages
A Brief History of Compilers
Further Reading
3. Arithmetic for Computers
3.1 Introduction
3.2 Addition and Subtraction
3.3 Multiplication
3.4 Division
3.5 Floating Point
3.6 Parallelism and Computer Arithmetic: Subword Parallelism
3.7 Real Stuff: Streaming SIMD Extensions and Advanced Vector Extensions in x86
3.8 Going Faster: Subword Parallelism and Matrix Multiply
3.9 Fallacies and Pitfalls
3.10 Concluding Remarks
Historical Perspective and Further Reading
3.12 Exercises
3. Solutions
Historical Perspective and Further Reading
The First Dispute
Diversity versus Portability
A Backward Step
The People Who Built the Bombs
Making the World Safe for Floating Point, or Vice Versa
The First IEEE 754 Chips
IEEE 754 Today
Further Reading
4. The Processor
4.1 Introduction
4.2 Logic Design Conventions
4.3 Building a Datapath
4.4 A Simple Implementation Scheme
4.5 An Overview of Pipelining
4.6 Pipelined Datapath and Control
4.7 Data Hazards: Forwarding versus Stalling
4.8 Control Hazards
4.9 Exceptions
4.10 Parallelism via Instructions
4.11 Real Stuff: The ARM Cortex-A8 and Intel Core i7 Pipelines
4.12 Going Faster: Instruction-Level Parallelism and Matrix Multiply
Advanced Topic: an Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations
4.14 Fallacies and Pitfalls
4.15 Concluding Remarks
Historical Perspective and Further Reading
4.17 Exercises
4. Solutions
An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations
Using Verilog for Behavioral Specification with Simulation for the 5-Stage Pipeline
Implementing Forwarding in Verilog
The Behavioral Verilog with Stall Detection
Implementing the Branch Hazard Logic in Verilog
Using Verilog for Behavioral Specification with Synthesis
More Illustrations of Instruction Execution on the Hardware
No Hazard Illustrations
More Examples
Forwarding Illustrations
Illustrating Pipelines with Stalls and Forwarding
Historical Perspective and Further Reading
Improving Pipelining Effectiveness and Adding Multiple Issue
Compiler Technology for Exploiting ILP
Further Reading
5. Large and Fast: Exploiting Memory Hierarchy
5.1 Introduction
5.2 Memory Technologies
5.3 The Basics of Caches
5.4 Measuring and Improving Cache Performance
5.5 Dependable Memory Hierarchy
5.6 Virtual Machines
5.7 Virtual Memory
5.8 A Common Framework for Memory Hierarchy
5.9 Using a Finite-State Machine to Control a Simple Cache
5.10 Parallelism and Memory Hierarchy: Cache Coherence
Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks
Advanced Material: Implementing Cache Controllers
5.13 Real Stuff: The ARM Cortex-A8 and Intel Core i7 Memory Hierarchies
5.14 Going Faster: Cache Blocking and Matrix Multiply
5.15 Fallacies and Pitfalls
5.16 Concluding Remarks
Historical Perspective and Further Reading
5.18 Exercises
5. Solutions
Parallelism and the Memory Hierarchy: Redundant Arrays of Inexpensive Disks
No Redundancy (RAID 0)
Mirroring (RAID 1)
Error Detecting and Correcting Code (RAID 2)
Bit-Interleaved Parity (RAID 3)
Block-Interleaved Parity (RAID 4)
Distributed Block-Interleaved Parity (RAID 5)
P+Q Redundancy (RAID 6)
RAID Summary
Advanced Material: Implementing Cache Controllers
SystemVerilog of a Simple Cache Controller
Basic Coherent Cache Implementation Techniques
An Example Cache Coherency Protocol
Implementing Snoopy Cache Coherence
Historical Perspective and Further Reading
The Development of Memory Hierarchies
Disk Storage
A Very Brief History of Flash Memory
A Brief History of Databases
RAID
Protection Mechanisms
A Brief History of Modern Operating Systems
Further Reading
6. Parallel Processors from Client to Cloud
6.1 Introduction
6.2 The Difficulty of Creating Parallel Processing Programs
6.3 SISD, MIMD, SIMD, SPMD, and Vector
6.4 Hardware Multithreading
6.5 Multicore and Other Shared Memory Multiprocessors
6.6 Introduction to Graphics Processing Units
6.7 Clusters, Warehouse Scale Computers, and Other Message-Passing Multiprocessors
6.8 Introduction to Multiprocessor Network Topologies
Communicating to the Outside World: Cluster Networking
6.10 Multiprocessor Benchmarks and Performance Models
6.11 Real Stuff: Benchmarking and Rooflines of the Intel Core i7 960 and the NVIDIA Tesla GPU
6.12 Going Faster: Multiple Processors and Matrix Multiply
6.13 Fallacies and Pitfalls
6.14 Concluding Remarks
Historical Perspective and Further Reading
6.16 Exercises
6. Solutions
Communicating to the Outside World: Cluster Networking
The Role of the Operating System in Networking
Improving Network Performance
Historical Perspective and Further Reading
SIMD Computers: Attractive Idea, Many Attempts, No Lasting Successes
Multimedia Extensions as SIMD Extensions to Instruction Sets
Other Early Experiments
Great Debates in Parallel Processing
More Recent Advances and Developments
Looking Further
Further Reading
Appendix A. Assemblers, Linkers, and the SPIM Simulator
Abstract
A.1 Introduction
A.2 Assemblers
A.3 Linkers
A.4 Loading
A.5 Memory Usage
A.6 Procedure Call Convention
A.7 Exceptions and Interrupts
A.8 Input and Output
A.9 SPIM
A.10 MIPS R2000 Assembly Language
A.11 Concluding Remarks
A.12 Exercises
Further Reading
Appendix B. The Basics of Logic Design
Abstract
B.1 Introduction
B.2 Gates, Truth Tables, and Logic Equations
B.3 Combinational Logic
B.4 Using a Hardware Description Language
B.5 Constructing a Basic Arithmetic Logic Unit
B.6 Faster Addition: Carry Lookahead
B.7 Clocks
B.8 Memory Elements: Flip-Flops, Latches, and Registers
B.9 Memory Elements: SRAMs and DRAMs
B.10 Finite-State Machines
B.11 Timing Methodologies
B.12 Field Programmable Devices
B.13 Concluding Remarks
B.14 Exercises
Further Reading
Appendix C. Graphics and Computing GPUs
Abstract
C.1 Introduction
C.2 GPU System Architectures
C.3 Programming GPUs
C.4 Multithreaded Multiprocessor Architecture
C.5 Parallel Memory System
C.6 Floating-point Arithmetic
C.7 Real Stuff: The NVIDIA GeForce 8800
C.8 Real Stuff: Mapping Applications to GPUs
C.9 Fallacies and Pitfalls
C.10 Concluding Remarks
C.11 Historical Perspective and Further Reading
Further Reading
Appendix D. Mapping Control to Hardware
Abstract
D.1 Introduction
D.2 Implementing Combinational Control Units
Mapping the ALU Control Function to Gates
Mapping the Main Control Function to Gates
D.3 Implementing Finite-State Machine Control
A ROM Implementation
A PLA Implementation
D.4 Implementing the Next-State Function with a Sequencer
Optimizing the Control Implementation
D.5 Translating a Microprogram to Hardware
Organizing the Control to Reduce the Logic
D.6 Concluding Remarks
D.7 Exercises
Appendix E. A Survey of RISC Architectures for Desktop, Server, and Embedded Computers
Abstract
E.1 Introduction
E.2 Addressing Modes and Instruction Formats
E.3 Instructions: the MIPS Core Subset
MIPS Core Instructions
Compare and Conditional Branch
E.4 Instructions: Multimedia Extensions of the Desktop/Server RISCs
E.5 Instructions: Digital Signal-Processing Extensions of the Embedded RISCs
E.6 Instructions: Common Extensions to MIPS Core
E.7 Instructions Unique to MIPS-64
Nonaligned Data Transfers
Remaining Instructions
E.8 Instructions Unique to Alpha
Remaining Instructions
E.9 Instructions Unique to SPARC v.9
Register Windows
Fast Traps
Support for LISP and Smalltalk
Overlapped Integer and Floating-Point Operations
Remaining Instructions
E.10 Instructions Unique to PowerPC
Branch Registers: Link and Counter
Remaining Instructions
E.11 Instructions Unique to PA-RISC 2.0
Nullification
A Cornucopia of Conditional Branches
Synthesized Multiply and Divide
Decimal Operations
Remaining Instructions
E.12 Instructions Unique to ARM
Remaining Instructions
E.13 Instructions Unique to Thumb
E.14 Instructions Unique to SuperH
E.15 Instructions Unique to M32R
E.16 Instructions Unique to MIPS-16
E.17 Concluding Remarks

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