Computer Architecture A Quantitative Approach 5th edition by John Hennessy, David Patterson ISBN 012383872X 978-8178672663
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Authors:John L. Hennessy; David A. Patterson , Series:IT & Computer [495] , Tags:Computers; Computer Architecture; General; Computer Architecture: A Quantitative Approach; Fifth Edition (2012) 857pp. 978-0-12-383872-8 , Author sort:Hennessy, John L. & Patterson, David A. , Ids:Google; 9780128119068 , Languages:Languages:eng , Published:Published:Nov 2017 , Publisher:Morgan Kaufmann , Comments:Comments:Computer Architecture: A Quantitative Approach, Sixth Edition has been considered essential reading by instructors, students and practitioners of computer design for over 20 years. The sixth edition of this classic textbook from Hennessy and Patterson, winners of the 2017 ACM A.M. Turing Award recognizing contributions of lasting and major technical importance to the computing field, is fully revised with the latest developments in processor and system architecture. The text now features examples from the RISC-V (RISC Five) instruction set architecture, a modern RISC instruction set developed and designed to be a free and openly adoptable standard. It also includes a new chapter on domain-specific architectures and an updated chapter on warehouse-scale computing that features the first public information on Google’s newest WSC. True to its original mission of demystifying computer architecture, this edition continues the longstanding tradition of focusing on areas where the most exciting computing innovation is happening, while always keeping an emphasis on good engineering design. Winner of a 2019 Textbook Excellence Award (Texty) from the Textbook and Academic Authors Association Includes a new chapter on domain-specific architectures, explaining how they are the only path forward for improved performance and energy efficiency given the end of Moore’s Law and Dennard scaling Features the first publication of several DSAs from industry Features extensive updates to the chapter on warehouse-scale computing, with the first public information on the newest Google WSC Offers updates to other chapters including new material dealing with the use of stacked DRAM; data on the performance of new NVIDIA Pascal GPU vs. new AVX-512 Intel Skylake CPU; and extensive additions to content covering multicore architecture and organization Includes “Putting It All Together” sections near the end of every chapter, providing real-world technology examples that demonstrate the principles covered in each chapter Includes review appendices in the printed text and additional reference appendices available online Includes updated and improved case studies and exercises ACM named John L. Hennessy and David A. Patterson, recipients of the 2017 ACM A.M. Turing Award for pioneering a systematic, quantitative approach to the design and evaluation of computer architectures with enduring impact on the microprocessor industry
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ISBN 10: 012383872X
ISBN 13: 978-8178672663
Author: John Hennessy, David Patterson
The computing world today is in the middle of a revolution: mobile clients and cloud computing have emerged as the dominant paradigms driving programming and hardware innovation today. The Fifth Edition of Computer Architecture focuses on this dramatic shift, exploring the ways in which software and technology in the cloud are accessed by cell phones, tablets, laptops, and other mobile computing devices. Each chapter includes two real-world examples, one mobile and one datacenter, to illustrate this revolutionary change. Updated to cover the mobile computing revolution Emphasizes the two most important topics in architecture today: memory hierarchy and parallelism in all its forms. Develops common themes throughout each chapter: power, performance, cost, dependability, protection, programming models, and emerging trends (“What’s Next”) Includes three review appendices in the printed text. Additional reference appendices are available online. Includes updated Case Studies and completely new exercises.
Computer Architecture: A Quantitative Approach 5th Table of contents:
Part I: Fundamentals of Computer Design
Chapter 1: Fundamentals of Computer Design
1.1. Introduction
1.2. Performance Metrics
1.3. Computer Design Challenges
1.4. Amdahl’s Law
1.5. Quantifying Performance
1.6. Trends in Technology
1.7. Cost Performance Trade-offs
1.8. A Brief History of Computer Architecture
Chapter 2: Instruction Set Design
2.1. Introduction
2.2. Instruction Set Architecture (ISA)
2.3. Instructions and Addressing Modes
2.4. RISC vs. CISC Architectures
2.5. Example Architectures: MIPS and x86
2.6. Design Principles for ISAs
2.7. Impact of Instruction Set Design on Performance
2.8. Modern Trends in ISA Design
Chapter 3: Pipelining
3.1. Introduction to Pipelining
3.2. Pipeline Stages
3.3. Hazards in Pipelines
3.4. Pipeline Performance
3.5. Superscalar and VLIW Pipelines
3.6. Pipelining and Instruction-Level Parallelism (ILP)
3.7. Real-World Pipeline Implementations
Part II: Memory Systems
Chapter 4: Memory Hierarchy Design
4.1. Introduction to Memory Hierarchy
4.2. Types of Memory: Register, Cache, Main Memory, and Disk
4.3. Cache Design: Structure and Optimization
4.4. Locality of Reference: Temporal and Spatial
4.5. Cache Replacement Policies
4.6. Virtual Memory and Paging
4.7. DRAM and SRAM Technology
4.8. Memory Consistency Models
4.9. Case Study: Modern Cache Architectures
Chapter 5: Virtual Memory
5.1. Overview of Virtual Memory
5.2. Address Translation: Page Tables
5.3. Virtual to Physical Address Mapping
5.4. TLB and its Role in Performance
5.5. Page Replacement Algorithms
5.6. Demand Paging and Thrashing
5.7. Memory Protection and Isolation
5.8. Memory Virtualization in Modern Systems
Part III: Parallelism
Chapter 6: Introduction to Parallelism
6.1. Types of Parallelism: Data vs. Task Parallelism
6.2. SIMD, MIMD, and SISD Architectures
6.3. Parallel Computing Models: Shared Memory vs. Distributed Memory
6.4. Amdahl’s Law and Its Implications for Parallelism
6.5. Parallelism in Modern Processors
6.6. Scaling in Multiprocessor Systems
Chapter 7: Instruction-Level Parallelism
7.1. Dynamic Instruction Scheduling
7.2. Superscalar Execution
7.3. Branch Prediction
7.4. Out-of-Order Execution
7.5. Speculative Execution
7.6. Limitations on Instruction-Level Parallelism
7.7. Case Study: Intel and AMD Processor Designs
Chapter 8: Thread-Level Parallelism
8.1. Multi-core Architectures
8.2. Shared Memory vs. Distributed Memory Architectures
8.3. Thread Synchronization
8.4. Locks and Barriers
8.5. Performance of Thread-Level Parallelism
8.6. Programming Models for Multi-core Processors
Chapter 9: Memory-Level Parallelism
9.1. Memory Latency Hiding Techniques
9.2. Memory Interleaving and Banked Memory
9.3. Cache Coherence and Synchronization
9.4. NUMA Architectures and Memory Access
9.5. Case Study: Multithreading in Memory Hierarchies
Part IV: Interconnection Networks and Storage
Chapter 10: Interconnection Networks
10.1. Interconnection Network Fundamentals
10.2. Network Topologies: Mesh, Hypercube, and Others
10.3. Routing in Interconnection Networks
10.4. Bisection Bandwidth and Latency
10.5. Interconnection in Parallel Computers
10.6. Network on Chip (NoC) Architectures
Chapter 11: Storage Systems
11.1. Overview of Storage Hierarchy
11.2. Magnetic Disks and Flash Storage
11.3. RAID and Fault Tolerance in Storage
11.4. Performance of Disk Systems
11.5. Network Storage: NAS and SAN
11.6. Cloud Storage and Distributed File Systems
Part V: Advanced Topics
Chapter 12: High-Performance Systems
12.1. Supercomputing Architectures
12.2. Vector and SIMD Processors
12.3. GPUs for General-Purpose Computing
12.4. Performance Optimization Techniques
12.5. Cloud Computing Architectures
12.6. Benchmarking High-Performance Systems
Chapter 13: Energy Efficiency in Computer Architecture
13.1. Power Consumption in Modern Processors
13.2. Energy-Efficient Design Principles
13.3. Dynamic Voltage and Frequency Scaling (DVFS)
13.4. Low-Power Design Techniques
13.5. Power vs. Performance Trade-offs
13.6. Energy Efficiency in Data Centers
Part VI: Case Studies
Chapter 14: Case Studies of Modern Architectures
14.1. Case Study: Intel and AMD Processors
14.2. Case Study: ARM Architecture
14.3. Case Study: IBM’s Power Architecture
14.4. Case Study: Graphics Processing Units (GPUs)
14.5. Case Study: Multi-core and Many-core Architectures
14.6. Case Study: Google’s Tensor Processing Units (TPUs)
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