Architecture of Computing Systems Arcs 2008 International Conference Dresden Germany February 25 28 2008 21st edition by Theo Ungerer, Christian Hochberger, Rainer G Spallek 3540781528 978-3540781523

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ISBN 10: 3540781528
ISBN 13: 978-3540781523
Author:  Theo Ungerer, Christian Hochberger, Rainer G Spallek

This book constitutes the refereed proceedings of the 21st International Conference on Architecture of Computing Systems, ARCS 2008, held in Dresden, Germany, in February 2008.

The 19 revised full papers presented together with 2 keynote papers were carefully reviewed and selected from 47 submissions. The papers cover a wide spectrum reaching from pre-fabrication adaptation of architectural templates to dynamic run-time adaptation of deployed systems with special focus on adaptivity and adaptive system architectures. The papers are organized in topical sections on hardware design, pervasive computing, network processors and memory management, reconfigurable hardware, real-time architectures, organic computing, and computer architecture.

Architecture of Computing Systems Arcs 2008 International Conference Dresden Germany February 25 28 2008  21st Table of contents:

1. Keynote: Grand Challenges of Computer Engineering
2. Keynote: The Impact of Operating Systems on Modern CPU Designs (and Vice Versa)
3. System Level Simulation of Autonomic SoCs with TAPES
4. Topology-Aware Replica Placement in Fault-Tolerant Embedded Networks
5. Design of Gate Array Circuits Using Evolutionary Algorithms
6. Direct Backtracking: An Advanced Adaptation Algorithm for Pervasive Applications
7. Intelligent Vehicle Handling: Steering and Body Postures While Cornering
8. A Hardware Packet Re-Sequencer Unit for Network Processors
9. Self-aware Memory: Managing Distributed Memory in an Autonomous Multi-master Environment
10. Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks
11. Synthesis of Multi-dimensional High-Speed FIFOs for Out-of-Order Communication
12. A Novel Routing Architecture for Field-Programmable Gate-Arrays
13. A Predictable Simultaneous Multithreading Scheme for Hard Real-Time

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