Computer Architecture A Quantitative Approach 4th Edition by Hennessy John L, Patterson David ISBN 0123704901 9780123704900

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ISBN 10: 0123704901 
ISBN 13: 9780123704900
Author: Hennessy  John L, Patterson David

The era of seemingly unlimited growth in processor performance is over: single chip architectures can no longer overcome the performance limitations imposed by the power they consume and the heat they generate. Today, Intel and other semiconductor firms are abandoning the single fast processor model in favor of multi-core microprocessors–chips that combine two or more processors in a single package. In the fourth edition of Computer Architecture, the authors focus on this historic shift, increasing their coverage of multiprocessors and exploring the most effective ways of achieving parallelism as the key to unlocking the power of multiple processor architectures. Additionally, the new edition has expanded and updated coverage of design topics beyond processor performance, including power, reliability, availability, and dependability.

Computer Architecture A Quantitative Approach 4th Table of contents:

1 Fundamentals of Computer Design
1.1 Introduction
1.2 Classes of Computers
1.3 Defining Computer Architecture
1.4 Trends in Technology
1.5 Trends in Power in Integrated Circuits
1.6 Trends in Cost
1.7 Dependability
1.8 Measuring, Reporting, and Summarizing Performance
1.9 Quantitative Principles of Computer Design
1.10 Putting It All Together: Performance and Price-Performance
1.11 Fallacies and Pitfalls
1.12 Concluding Remarks
1.13 Historical Perspectives and References
Case Studies with Exercises by Diana Franklin
2 Instruction-Level Parallelism and Its Exploitation
2.1 Instruction-Level Parallelism: Concepts and Challenges
2.2 Basic Compiler Techniques for Exposing ILP
2.3 Reducing Branch Costs with Prediction
2.4 Overcoming Data Hazards with Dynamic Scheduling
2.5 Dynamic Scheduling: Examples and the Algorithm
2.6 Hardware-Based Speculation
2.7 Exploiting ILP Using Multiple Issue and Static Scheduling
2.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation
2.9 Advanced Techniques for Instruction Delivery and Speculation
2.10 Putting It All Together: The Intel Pentium 4
2.11 Fallacies and Pitfalls
2.12 Concluding Remarks
2.13 Historical Perspective and References
Case Studies with Exercises by Robert P. Colwell
3 Limits on Instruction-Level Parallelism
3.1 Introduction
3.2 Studies of the Limitations of ILP
3.3 Limitations on ILP for Realizable Processors
3.4 Crosscutting Issues: Hardware versus Software Speculation
3.5 Multithreading: Using ILP Support to Exploit Thread-Level Parallelism
3.6 Putting It All Together: Performance and Efficiency in Advanced Multiple-Issue Processors
3.7 Fallacies and Pitfalls
3.8 Concluding Remarks
3.9 Historical Perspective and References
Case Study with Exercises by Wen-mei W. Hwu and John W. Sias
4 Multiprocessors and Thread-Level Parallelism
4.1 Introduction
4.2 Symmetric Shared-Memory Architectures
4.3 Performance of Symmetric Shared-Memory Multiprocessors
4.4 Distributed Shared Memory and Directory-Based Coherence
4.5 Synchronization: The Basics
4.6 Models of Memory Consistency: An Introduction
4.7 Crosscutting Issues
4.8 Putting It All Together: The Sun T1 Multiprocessor
4.9 Fallacies and Pitfalls
4.10 Concluding Remarks
4.11 Historical Perspective and References
Case Studies with Exercises by David A. Wood
5 Memory Hierarchy Design
5.1 Introduction
5.2 Eleven Advanced Optimizations of Cache Performance
5.3 Memory Technology and Optimizations
5.4 Protection: Virtual Memory and Virtual Machines
5.5 Crosscutting Issues: The Design of Memory Hierarchies
5.6 Putting It All Together: AMD Opteron Memory Hierarchy
5.7 Fallacies and Pitfalls
5.8 Concluding Remarks
5.9 Historical Perspective and References
Case Studies with Exercises by Norman P. Jouppi
6 Storage Systems
6.1 Introduction
6.2 Advanced Topics in Disk Storage
6.3 Definition and Examples of Real Faults and Failures
6.4 I/O Performance, Reliability Measures, and Benchmarks
6.5 A Little Queuing Theory
6.6 Crosscutting Issues
6.7 Designing and Evaluating an I/O System – The Internet Archive Cluster
6.8 Putting It All Together: NetApp FAS6000 Filer
6.9 Fallacies and Pitfalls
6.10 Concluding Remarks
6.11 Historical Perspective and References
Case Studies with Exercises by Andrea C. Arpaci-Dusseau and Remzi H. Arpaci-Dusseau
A Pipelining: Basic and Intermediate Concepts
A.1 Introduction
A.2 The Major Hurdle of Pipelining – Pipeline Hazards
A.3 How Is Pipelining Implemented?
A.4 What Makes Pipelining Hard to Implement?
A.5 Extending the MIPS Pipeline to Handle Multicycle Operations
A.6 Putting It All Together: The MIPS R4000 Pipeline
A.7 Crosscutting Issues
A.8 Fallacies and Pitfalls
A.9 Concluding Remarks
A.10 Historical Perspective and References
B Instruction Set Principles and Examples
B.1 Introduction
B.2 Classifying Instruction Set Architectures
B.3 Memory Addressing
B.4 Type and Size of Operands
B.5 Operations in the Instruction Set
B.6 Instructions for Control Flow
B.7 Encoding an Instruction Set
B.8 Crosscutting Issues: The Role of Compilers
B.9 Putting It All Together: The MIPS Architecture
B.10 Fallacies and Pitfalls
B.11 Concluding Remarks
B.12 Historical Perspective and References
C Review of Memory Hierarchy
C.1 Introduction
C.2 Cache Performance
C.3 Six Basic Cache Optimizations
C.4 Virtual Memory
C.5 Protection and Examples of Virtual Memory
C.6 Fallacies and Pitfalls
C.7 Concluding Remarks
C.8 Historical Perspective and References

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