Compilation Techniques for Reconfigurable Architectures 1st Edition by Joao Cardoso, Pedro C Diniz ISBN 038709671X 9780387096711

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ISBN 10: 038709671X 
ISBN 13: 9780387096711
Author: Joao Cardoso, Pedro C Diniz

The extreme ?exibility of recon?gurable architectures and their performance pot- tial have made them a vehicle of choice in a wide range of computing domains, from rapid circuit prototyping to high-performance computing. The increasing availab- ity of transistors on a die has allowed the emergence of recon?gurable architectures with a large number of computing resources and interconnection topologies. To – ploit the potential of these recon?gurable architectures, programmers are forced to map their applications, typically written in high-level imperative programming l- guages, such as C or MATLAB, to hardware-oriented languages such as VHDL or Verilog. In this process, they must assume the role of hardware designers and software programmers and navigate a maze of program transformations, mapping, and synthesis steps to produce ef?cient recon?gurable computing implementations. The richness and sophistication of any of these application mapping steps make the mapping of computations to these architectures an increasingly daunting process. It is thus widely believed that automatic compilation from high-level programming languages is the key to the success of recon?gurable computing. This book describes a wide range of code transformations and mapping te- niques for programs described in high-level programming languages, most – tably imperative languages, to recon?gurable architectures.

 Compilation Techniques for Reconfigurable Architectures 1st Table of contents:

Chapter 1: Introduction
1.1 The Promise of Reconfigurable Architectures and Systems
1.2 The Challenge: How to Program and Compilefor Reconfigurable Systems?
1.3 This Book: Key Techniques when Compilingto Reconfigurable Architecture
1.4 Organization of this Book
Chapter 2: Overview of Reconfigurable Architectures
2.1 Evolution of Reconfigurable Architectures
2.2 Reconfigurable Architectures: Key Characteristics
2.3 Granularity
2.3.1 Fine-Grained Reconfigurable Architectures
2.3.2 Coarse-Grained Reconfigurable Architectures
2.3.3 Hybrid Reconfigurable Architectures
2.3.4 Granularity and Mapping
2.4 Interconnection Topologies
2.5 System-Level Integration
2.6 Dynamic Reconfiguration
2.7 Computational and Execution Models
2.8 Streaming Data Input and Output
2.9 Summary
Chapter 3: Compilation and Synthesis Flows
3.1 Overview
3.1.1 Front-End
3.1.2 Middle-End
3.1.3 Back-End
3.2 Hardware Compilation and High-Level Synthesis
3.2.1 Generic High-Level Synthesis
3.2.2 Customized High-Level Synthesis for Fine-GrainedReconfigurable Architectures
3.2.3 Register-Transfer-Level/Logic Synthesis
3.2.4 High-Level Compilation for Coarse-GrainedReconfigurable Architectures
3.2.5 Placement and Routing
3.3 Illustrative Example
3.3.1 High-Level Source Code Example
3.3.2 Data-Flow Representation
3.3.3 Computation-Oriented Mapping and Scheduling
3.3.4 Data-Oriented Mapping and Transformations
3.3.5 Translation to Hardware
3.4 Reconfigurable Computing Issues and Their Impacton Compilation
3.4.1 Programming Languages and Execution Models
3.4.2 Intermediate Representations
3.4.3 Target Reconfigurable Architecture Features
3.5 Summary
Chapter 4: Code Transformations
4.1 Bit-Level Transformations
4.1.1 Bit-Width Narrowing
4.1.2 Bit-Level Optimizations
4.1.3 Conversion from Floating- to Fixed-Point Representations
4.1.4 Nonstandard Floating-Point Formats
4.2 Instruction-Level Transformations
4.2.1 Operator Strength Reduction
4.2.2 Height Reduction
4.2.3 Code Motion
4.3 Loop-Level Transformations
4.3.1 Loop Unrolling
4.3.2 Loop Tiling and Loop Strip-Mining
4.3.3 Loop Merging and Loop Distribution
4.4 Data-Oriented Transformations
4.4.1 Data Distribution
4.4.2 Data Replication
4.4.3 Data Reuse and Scalar Replacement in Registersand Internal RAMs
4.4.4 Other Data-Oriented Transformations
4.5 Function-Oriented Transformations
4.5.1 Function Inlining and Outlining
4.5.2 Recursive Functions
4.6 Which Code Transformations to Choose?
4.7 Summary
Chapter 5: Mapping and Execution Optimizations
5.1 Hardware Execution Techniques
5.1.1 Instruction-Level Parallelism
5.1.2 Speculative Execution
5.1.3 Predication and if-conversion
5.1.4 Multi Tasking
5.2 Partitioning
5.2.1 Temporal Partitioning
5.2.2 Spatial Partitioning
5.2.3 Illustrative Example
5.3 Mapping Program Constructs to Resources
5.3.1 Mapping Scalar Variables to Registers
5.3.2 Mapping of Operations to FUs
5.3.3 Mapping of Selection Structures
5.3.4 Sharing Functional Units FUs
5.3.5 Combining Instructions for RFUs
5.4 Pipelining
5.4.1 Pipelined Functional and Execution Units
5.4.2 Pipelining Memory Accesses
5.4.3 Loop Pipelining
5.4.4 Coarse-Grained Pipelining
5.4.5 Pipelining Configuration–Computation Sequences
5.5 Memory Accesses
5.5.1 Partitioning and Mapping of Arrays to Memory Resources
5.5.2 Improving Memory Accesses
5.6 Back-End Support
5.6.1 Allocation, Scheduling, and Binding
5.6.2 Module Generation
5.6.3 Mapping, Placement, and Routing
5.7 Summary
Chapter 6: Compilers for Reconfigurable Architectures
6.1 Early Compilation Efforts
6.2 Compilers for FPGA-Based Systems
6.2.1 The SPC Compiler
6.2.2 A C to Fine-Grained Pipelining Compiler
6.2.3 The DeepC Silicon Compiler
6.2.4 The COBRA-ABS Tool
6.2.5 The DEFACTO Compiler
6.2.6 The Streams-C Compiler
6.2.7 The Cameron Compiler
6.2.8 The MATCH Compiler
6.2.9 The Galadriel and Nenya Compilers
6.2.10 The Sea Cucumber Compiler
6.2.11 The Abstract-Machines Compiler
6.2.12 The CHAMPION Software Design Environment
6.2.13 The SPARCS Tool
6.2.14 The ROCCC Compiler
6.2.15 The DWARV Compiler
6.3 Compilers for Coarse-Grained Reconfigurable Architectures
6.3.1 The DIL Compiler
6.3.2 The RaPiD-C Compiler
6.3.3 The CoDe-X Compiler
6.3.4 The XPP-VC Compiler
6.3.5 The DRESC Compiler
6.4 Compilers for Hybrid Reconfigurable Architectures
6.4.1 The Chimaera-C Compiler
6.4.2 The Garp and the Nimble C Compilers
6.4.3 The NAPA-C Compiler
6.5 Compilation Efforts Summary
Chapter 7: Perspectives on Programming ReconfigurableComputing Platforms
7.1 How to Make Reconfigurable Computing a Reality?
7.1.1 Easy of Programming
7.1.2 Program Portability and Legacy Code Migration
7.1.3 Performance Portability
7.2 Research Directions in Compilation for ReconfigurableArchitectures
7.2.1 Programming Language Design
7.2.2 Intermediate Representation
7.2.3 Mapping to Multiple Computing Engines
7.2.4 Code Transformations
7.2.5 Design-Space Exploration and Compilation Time
7.2.6 Pipelined Execution
7.2.7 Memory Mapping Optimizations
7.2.8 Application-Specific Compilers and Cores
7.2.9 Resource Virtualization
7.2.10 Dynamic and Incremental Compilation
7.3 Tackling the Compilation Challenge for ReconfigurableArchitectures
7.4 Reconfigurable Architectures and Nanotechnology
7.5 Summary
Chapter 8: Final Remarks

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